1. Field of the Invention
The invention relates generally to a pumping circuit, and more particularly to, a pumping circuit wherein a program voltage and a program verify voltage of different levels are pumped using a program verify signal, thus reducing ripples and active current.
2. Description of the Prior Art
In the flash memory device, program, erase and read operations are performed according to the voltage applied to the word line of a selected cell, drain/source, and the substrate. In order to perform the program operation of the flash memory cell, it is required that a pumping voltage of about 9V higher a little than the power supply voltage be generated using a pumping circuit and a regulation circuit and the generated voltage be then applied to the word line of the selected cell. .
FIG. 1A shows a common pumping circuit that is used to program the flash memory cell. The construction of the pumping circuit in FIG. 1A will be below described.
A first NMOS transistor N11 driven by an enable signal (EN) is connected between the power supply terminal VDD and a first node Q11. A second NMOS transistor N12 is diode-connected between the first node Q11 and a second node Q12. A third NMOS transistor N13 is diode-connected between the second node Q12 and a third node Q13. A fourth NMOS transistor N14 is diode-connected between the third node Q13 and a fourth node Q14. A fifth NMOS transistor N15 is diode-connected between the fourth node Q14 and an output terminal VPPI. Further, the first˜fifth capacitors C11˜C15 that are charged according to first and second clock signals (CLK1 and CLK2) are connected to the nodes Q11˜Q14 and the output terminal VPPI, respectively. In other words, the first, third and fifth capacitors C11, C13 and C15 that are charged according to the first clock signal (CLK1) are connected to the first node Q11, the third node Q13 and output terminal VPPI, respectively. Also, the second and fourth capacitors C12 and C14 that are charged according to the second clock signal (CLK2) are connected to the second and fourth nodes Q12 and Q14, respectively.
A method of driving the pumping circuit constructed above will be described by reference to the operating waveform shown in FIG. 1B.
If the enable signal (EN) is applied as a HIGH state, the first NMOS transistor N11 is turned on. Thus, the power supply voltage (VDD) is applied and the first˜fifth capacitors C11˜C15 are charged according to the first and second clock signals (CLK1 and CLK2) having opposite phases, respectively, so that the voltage of the respective node is raised. In other words, the first, third and fifth capacitors C11, C13 and C15 are charged according to the first clock signal (CLK1), so that the first and third nodes Q11 and Q13 and the output terminal VPPI are raised to a given voltage. Further, the second and fourth capacitors C12 and C14 are also charged according to the second clock signal (CLK2), so that the second and fourth nodes Q12 and Q14 are raised to a given voltage. The voltage of the node raised such is transferred to a next stage through the second˜fifth NMOS transistors N12˜N15 that are diode-connected. Finally, the output terminal VPPI keeps a given voltage, which is determined by the power supply voltage (VDD) and the number and capacity of the capacitor.
However, in order to program the flash memory cell, the program verify operation is performed to very whether the selected cell is programmed. The program operation is again performed depending on the result of the verification. The program and program verify operations are repeatedly performed by a set times. At this time, in order to perform the program verify operation, it is required to apply the program verify voltage of about 6V to the word line of the cell. The program verify voltage is one generated by a regulation circuit that changes a regulation level of the pumping voltage of about 9V generated in the pumping circuit. Therefore, as the pumping voltage must be regulated as the program verify level using the pumping circuit for generating the program voltage, many ripples may occur and the active current is also increased.
FIG. 2 is a graph illustrating the ripples generating when the program verify voltage is regulated using the pumping circuit for generating the program voltage. The ripples in this program verify operation may give rise to confusion in determining whether the program operation of the cell is successful or failed. If the worst, an erroneous operation determining that the failed cell is successful as a result of the program verify operation may be generated.